Embedded

FPGA Clock Schemes

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.
EDN

Clock sources with integrated power supply noise rejection simplify power supply design in FPGA-based systems

Power hungry systems cannot be free of power supply noise. In general, system designers try to use low noise linear power supplies whenever possible. However, excessive power dissipation usually ...
Electronic Specifier

DigiKey at embedded world 2026 with Red Pitaya

At embedded world, on the DigiKey booth, Paige Hookway speaks with Miha Gjura at Red Pitaya, about new ways for multichannel synchronisation.
Electronic Design

First-Time FPGA Success Requires Exhaustive Examination of Clock Domain Crossings

Clock domain crossings are significant sources of field system failures. Despite this fact, designs continue to be released without fully verified CDCs. A false sense of security resulting from ...
Electronic Design

Interfacing FPGAs to an ADC’s Digital Data Output

Different types of interface standards used in LVDS. Recommendations for interfacing FPGAs to ADCs. Methods of troubleshooting when connecting to the AD9268 ADC. 1. Multiple interface possibilities ...
Hackaday

Taking The Pulse (Width Modulation) Of An FPGA

Use the FPGA as a CPU which allows you to add predefined I/O blocks Build custom peripherals for an external CPU from predefined I/O blocks Build custom logic circuitry from scratch Projects that ...
EDN

Practical clocking considerations for high-speed ADC design

Among many deliberations when designing with high-speed analog-to-digital converters (ADCs), the effect of the ADC’s sampling clock is paramount to meeting specific design requirements. There are ...